FIG. 1 illustrates a hardware implementation of graphics processing solution developed for Notebook Computer technology by the Nvidia Corporation, which is known by the product name of Optimus™ An Integrated Graphics Processor (IGP) chip includes a central processing unit (CPU), graphics processing unit (GPU), and a memory controller hub (MCH). A Platform Controller Hub (PCH) may be optionally included to support driving displays with different interface standards, such as LVDS, VGA, and DP/HDMI. As illustrative examples, the IGP chip may be an Intel chip such as the Intel core 15 or core 17 chips. Alternatively the IGP chip may be an AMD A4, A6, A10, or A8 chip. The IGP chip is coupled to a system memory.
A discrete GPU (dGPU) is coupled to the IGP via a Peripheral Component Interface (PCIe) link. The dGPU may, for example, be an Nvidia GPU. The dGPU is coupled to a local memory.
As illustrated in FIG. 2, the process flow may be varied to have either the dGPU 201 or the IGP 202 render the graphics image. An application is launched 205 and a routing decision 210 is made regarding which processor will perform the rendering of a frame 220. If the dGPU is used, the dGPU is used for the rendering and a fast GPU initiation is implemented 215. A copy engine 218 in the dGPU may be used to facilitate copying the rendered image to the system memory of the IGP. Display hardware 250 in the IGP displays the rendered frames on a display 260. The process flow has the routing selected to achieve the best performance or best battery life depending on application. The dGPU has the advantage of superior graphics processing capabilities with respect to the IGP. However, using the dGPU also consumes more power than rendering images with the IGP. Consequently, battery lifetime is reduced when the dGPU is used to render images. In mobile environments, the process flow is selected so that the dGPU is activated and used to render only the more demanding graphics processing operations, such as games, media, and GPU computing. The dGPU is shut off when there are less demanding graphics processing operations that can be handled by the IGP, such as processing the graphics of documents and surfing the Web.
When the dGPU is utilized to render images, a blit operation occurs to transfer the final displayable buffer to the system memory of the IGP, and then the IGP provides the rendered image to a display. This blit operation is performed via the PCIe interface.
The inventor of the present application has discovered that several industry trends may make it difficult to continue to use the Optimus™ solution in the future, at least for the low-cost end of the market. First, one trend is that displays are increasing in resolution over time, which in turn means that the amount of data per frame is increasing. Second, there are cost pressures on IC companies to reduce the bandwidth of the PCIe bus. For example, to reduce costs, Intel has reduced the PCIe bandwidth from sixteen lanes to four lanes for some IGPs. The PCIe bandwidth might even be reduced to two lanes at some point in the future. If these two trends continue, then at some point in time there will be insufficient bandwidth for the blit operation to be performed at acceptable frame rates, at least for the lower-cost IGPs.
Thus, what is desired are new approaches to operate a multi-graphics processing system having an IGP and a dGPU.